一种基于Avalon总线PCI从设备IP核设计

在工程实践中，如何实现上位机与Qsys系统之间的无缝链接，一直是设计中的重点。针对以上问题，本文提出了基于Avalon总线的PCI从设备IP核的设计方法，以嵌入式IP软核的形式取代原有专用接口芯片。设计按照自顶而下设计流程，首先给出了PCI从设备的RTL级模块划分，并详细设计了其mealy型状态机，然后将Avalon总线与PCI总线实现片内互联，最终开发了一个具有自主知识产权的IP软核。该IP核符合PCI 2.2标准，可进行资源自动配置，实现数据正确读写，还实现了PCI总线与Nios II处理器之间的数据传输，验证了该设计的正确性和可行性。

IP core design of PCI slave interface based on Avalon bus

How to realize the seamless link between the PC and the Qsys system has always been the focus of a design in the engineering practice. In view of the above problem, this paper presents an IP core design of PCI slave interface based on Avalon bus, which replaces the original design method of using special interface chip, in form of embedded IP core. The design is according to the top down design process, firstly gives the RTL level module partition of the PCI slave interface, and carefully designs the mealy type of state machine. Then completes the on chip interconnection between Avalon bus and PCI bus. Finally develops an IP soft core with independent intellectual property rights, and validates the feasibility of the design in engineering practice.