Multidimensional Test Escape Rate Modeling |
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| Authors: | Butler K.M. Carulli J.M. Saxena J. Nahar A. Daasch W.R. |
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| Affiliation: | Texas Instrum., Dallas, TX, USA; |
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| Abstract: | Today's SoC designs contain many types of circuitry, each with various test types. This article revisits the classic test escape models and highlights their limitations in a test environment with different types of circuits and different test types with overlapping coverage. A new methodology for test escape rate prediction is presented. |
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