| 一种降低电路泄漏功耗的多阈值电压方法 |
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| 引用本文： | 张姚,易茂祥,王可可,吴清焐,丁力,梁华国.一种降低电路泄漏功耗的多阈值电压方法[J].微电子学,2018,48(6):839-845. |
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| 作者姓名： | 张姚 易茂祥 王可可 吴清焐 丁力 梁华国 |
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| 作者单位： | 合肥工业大学 电子科学与应用物理学院, 合肥 230009,合肥工业大学 电子科学与应用物理学院, 合肥 230009,合肥工业大学 电子科学与应用物理学院, 合肥 230009,合肥工业大学 电子科学与应用物理学院, 合肥 230009,合肥工业大学 电子科学与应用物理学院, 合肥 230009,合肥工业大学 电子科学与应用物理学院, 合肥 230009 |
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| 基金项目： | 国家自然科学基金面上项目(61371025,61674048) |
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| 摘 要： | 目前,多阈值电压方法是缓解电路泄漏功耗的有效手段之一。但是,该方法会加重负偏置温度不稳定性(NBTI)效应,导致老化效应加剧,引起时序违规。通过找到电路的潜在关键路径集合,运用协同优化算法,将关键路径集合上的门替换为低阈值电压类型,实现了一种考虑功耗约束的多阈值电压方法。基于45 nm工艺模型及ISCAS85基准电路的仿真结果表明,在一定功耗约束下,该方法的时延改善率最高可达12.97%,明显优于常规多阈值电压方法。电路的规模越大,抗泄漏功耗的效果越好。
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| 关 键 词： | 负偏置温度不稳定性 泄漏功耗 多阈值电压 |
| 收稿时间： | 2018/1/14 0:00:00 |
A Multi-Threshold Voltage Method for Alleviating Circuit Leakage Power Consumption |
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| ZHANG Yao,YI Maoxiang,WANG Keke,WU Qingwu,DING Li and LIANG Huaguo.A Multi-Threshold Voltage Method for Alleviating Circuit Leakage Power Consumption[J].Microelectronics,2018,48(6):839-845. |
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| Authors: | ZHANG Yao YI Maoxiang WANG Keke WU Qingwu DING Li and LIANG Huaguo |
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| Affiliation: | School of Electronic Science and Applied Physics, Hefei University of Technology, Hefei 230009, P. R. China,School of Electronic Science and Applied Physics, Hefei University of Technology, Hefei 230009, P. R. China,School of Electronic Science and Applied Physics, Hefei University of Technology, Hefei 230009, P. R. China,School of Electronic Science and Applied Physics, Hefei University of Technology, Hefei 230009, P. R. China,School of Electronic Science and Applied Physics, Hefei University of Technology, Hefei 230009, P. R. China and School of Electronic Science and Applied Physics, Hefei University of Technology, Hefei 230009, P. R. China |
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| Abstract: | The multi-threshold voltage method is an effective way to alleviate the circuit leakage power consumption today. However, the influence of negative bias temperature instability(NBTI) on the circuit was aggravated with the multi-threshold voltage method. NBTI will exacerbate the aging effect and lead to timing violation. According to the preset timing margin, the potential critical paths could be found and the gates in these paths could be replaced with the low threshold voltage type through the collaborative optimization algorithm. Thus, a multi-Vth method considering power constraints for mitigating circuit aging was proposed. Experimental results based on 45 nm process model and ISCAS85 benchmark circuits showed that the after-aging delay improvement was up to 12.97% with the power constraints, which was obviously better than the existing multi-threshold voltage schemes. In addition, the anti-aging effect could be better if the integration scale of the circuit was larger. |
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