45nm工艺pn混合下拉网络多米诺异或门设计

提出了一种pn混合下拉网络技术，即在多米诺门的下拉网络中混合使用pMOS管和nMOS管来降低电路的功耗并提高电路的性能. 首先，应用此技术设计了多米诺异或门，与标准的n型多米诺异或门相比，新型异或门的静态功耗和动态功耗分别减小了46%和3%. 然后，在此技术的基础上，综合应用多电源电压技术和双阈值技术设计了功耗更低的多米诺异或门，与标准的n型多米诺异或门相比，静态功耗和动态功耗分别减小了82%和21%. 最后分析并确定了4种多米诺异或门的最小漏电流状态和交流噪声容限.

Design of pn Mixed Pull-Down Network Domino XOR Gate in 45nm Technology

A pn mixed pull-down network technique is proposed, based on the application of pMOS transistor and nMOS transistor in the pull-down network,to lower the power and improve the performance of the domino circuits.First,a domino XOR gate with this technique is designed.Compared to the standard N type domino XOR gate,its static power and dynamic power are reduced by up to 46% and 3%,respectively.Second,using this technique,the dual-threshold voltage techniques and the multiple supply voltages techniques,a novel domino XOR gate is present and its static power and dynamic power are reduced by up to 82% and 21%,as compared to the standard N type domino XOR gate.At last,the minimum static power state of four XOR gates and AC noise margins are analyzed and obtained thoroughly.