| H.264帧内预测和模式判断的并行硬件结构设计 |
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| 引用本文： | 张刚,苏海冰.H.264帧内预测和模式判断的并行硬件结构设计[J].电视技术,2009,33(1). |
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| 作者姓名： | 张刚 苏海冰 |
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| 作者单位： | 1. 中国科学院,光电技术研究所,四川,成都,610209;中国科学院研究生院,北京,100039
2. 中国科学院,光电技术研究所,四川,成都,610209 |
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| 摘 要： | 针对H.264视频压缩编码算法中帧内预测和模式判断模块,分析并提出了一种高并行度的FPGA实现方法.完成了硬件结构的设计和验证.用VHDL实现本设计,综合后电路最大延迟为8.34 ns.仿真及综合结果表明.该设计能够完全满足高清数字视频的实时处理要求.
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| 关 键 词： | H.264标准 帧内预测 模式判断 并行 可编程门阵列 |
Design of Parallel Hardware Architecture for H.264 Intra Prediction and Mode Decision |
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| ZHANG Gang,SU Hai-bing.Design of Parallel Hardware Architecture for H.264 Intra Prediction and Mode Decision[J].Tv Engineering,2009,33(1). |
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| Authors: | ZHANG Gang SU Hai-bing |
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| Affiliation: | 1.Institute of Optics and Electronics;Chinese Academy of Sciences;Chengdu 610209;China;2.Graduate School of CAS;Beijing 100039;China |
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| Abstract: | A high-parellel hardware implementation method for intra prediction and mode decision of H.264 oriented to FPGA is analysed and proposed, and its hardware architecture design and verification are completed.The design is implemented by VHDL, and the longest path delay is 8.34 ns in the experimental results.The simulation and synthesis results show that the design can fully satisfy the constraint of real-time processing required by high-definition digital video. |
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| Keywords: | H 264 intra prediction mode decision parallel FPGA |
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