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Test program synthesis for modules and chips having boundary scan |
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| Authors: | Jung-Cheun Lien Melvin A Breuer |
| Affiliation: | (1) Department of Electrical Engineering—Systems, University of Southern California, 90089-2560 Los Angeles, CA;(2) Present address: Actel Corporation, Sunnyvale, CA |
| Abstract: | |
| Keywords: | Board and system test boundary scan built-in self-test design-for-test test controllers test program synthesis |
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