| 一种快速浮点乘法单元的设计与实现 |
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| 引用本文： | 杜慧敏,马超.一种快速浮点乘法单元的设计与实现[J].西安邮电学院学报,2013(1):62-66,0. |
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| 作者姓名： | 杜慧敏 马超 |
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| 作者单位： | 西安邮电大学电子工程学院 |
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| 基金项目： | 国家自然科学基金重点资助项目(90607008);陕西省工业攻关基金资助项目(2011K06K-47) |
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| 摘 要： | 以自主设计的图形处理单元(Graphic Processing Unit,GPU)所需求的浮点乘法处理能力为目标,设计并实现了6级全流水线的单精度浮点乘法器,其部分积生成采用修正的Booth编码算法,部分积压缩采用4-2和3-2混合Wallace树结构。使用Synopsys的VCS完成待测设计的功能验证,使用Design Complier工具在0.13um工艺库下实现设计综合,可以达到2.7Gflops的处理速度,符合图形处理器的要求。
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| 关 键 词： | 浮点乘法 Booth编码 部分积压缩 DC综合 |
Design and implementation of a high speed floating-point multiply unit |
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| DU Huimin,MA Chao.Design and implementation of a high speed floating-point multiply unit[J].Journal of Xi'an Institute of Posts and Telecommunications,2013(1):62-66,0. |
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| Authors: | DU Huimin MA Chao |
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| Affiliation: | (School of Electronics Engineering,Xi’an University of Posts and Telecomunications,Xi’an 710121,China) |
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| Abstract: | Floating-point multiplication unit has been widely used in Scientific Computing,Digital Signal Processing,Video Image Processing,and Graphic Processing.The single precision floatingpoint multiplier including 6level full pipeline was designed and implemented based on floating-point multiplication processing power needed by graphics processing unit.The modified booth algorithm was used in the partial product formation.The 4-2and 3-2mixed Wallace tree structure was employed in the partial product compression.By using Synopsys’s VCS to complete the function verification of the design under test and DC to synthesize the design under the 0.13um process library,the processing speed can reach 2.7Gflops,which met the requirements of the graphic processor. |
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| Keywords: | floating-point multiply Booth encoder partial product compression DC synthesize |
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