Novel Low-$k$ Dielectric Buried-Layer High-Voltage LDMOS on Partial SOI |
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| Authors: | Luo X. Wang Y. Deng H. Fan J. Lei T. Liu Y. |
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| Affiliation: | State key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu, China; |
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| Abstract: | A high-voltage lateral double diffused metal–oxide–semiconductor transistor on partial silicon on insulator (PSOI) with a buried low-$k$ dielectric (LK PSOI) is proposed. The low-$k$ value enhances the electric field strength in the dielectric $(E_{I})$. The Si window not only makes the substrate share the breakdown voltage (BV) and modulates the field distribution in the SOI layer but also alleviates the self-heating effect. Compared with those of the conventional PSOI, the $E_{I}$ and BV of LK PSOI with $k_{I} = hbox{2}$ are enhanced by 74% and 19%, respectively. |
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