Design of CMOS three-stage amplifiers for fast-settling switched-capacitor circuits

In this paper, a time-domain design procedure for fast-settling three-stage amplifiers is presented. In the proposed design approach, the amplifier is designed to settle within a specific time with a given settling accuracy and circuit noise budget by optimizing both the power consumption and silicon die area. Both linear and nonlinear settling regions of three-stage amplifiers are considered and optimal values of the amplifier stages transconductance and compensation capacitors are obtained using the genetic algorithm optimization. Detailed design equations are provided and circuit level simulation results using a 90 nm CMOS technology are presented to evaluate the usefulness of the proposed design scheme respected to the previously reported design approaches.