65nm工艺下20Gb/s无电感限幅放大器设计与分析

本文设计了一款能工作在20Gb/s速率下的无电感限幅放大器。限幅放大器包括三各部分：带直流失调消除的输入匹配级，增益级和输出驱动级。本设计采用交叉负反馈技术，使得放大器在获得高带宽的同时拥有较为平坦的频率响应。直流失调消除环路中增加了误差放大器来保证直流失调消除效果。放大器在65纳米工艺下成功流片，芯片面积为0.45 × 0.25平方毫米（不包括PAD），测试结果显示放大器的差分增益为37dB，带宽为16.5GHz，在高达26.5GHz的频率内Sdd11和Sdd22分别小于-16dB和-9dB。除了驱动级，整个放大器在1.2V的电源电压下消耗50mA的电流。

Design and analysis of 20 Gb/s inductorless limiting amplifier in 65 nm CMOS technology

A high speed inductorless limiting amplifier (LA) in an optical communication receiver with the working speed up to 20 Gb/s is presented. The LA includes an input matching network, a four-stage 3rd order amplifier core, an output buffer for the test and a DC offset cancellation (DCOC). It uses the active interleaving feedback technique both to broaden the bandwidth and achieve the flatness response. Based on our careful analysis of the DCOC and stability, an error amplifier is added to the DCOC loop in order to keep the offset voltage reasonable. Fabricated in the 65 nm CMOS technology, the LA only occupies an area of 0.45 × 0.25 mm² (without PAD). The measurement results show that the LA achieves a differential voltage gain of 37 dB, and a 3-dB bandwidth of 16.5 GHz. Up to 26.5 GHz, the S_dd11 and S_dd22 are less than -16 dB and -9 dB. The chip excluding buffer is supplied by 1.2 V VDD and draws a current of 50 mA.