| IEEE 1394b VersaPHY的IP核设计与实现 |
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| 引用本文： | 朱榆涵,邵洪峰,伊小素,龙映雪.IEEE 1394b VersaPHY的IP核设计与实现[J].计算机测量与控制,2012,20(9):2525-2528. |
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| 作者姓名： | 朱榆涵 邵洪峰 伊小素 龙映雪 |
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| 作者单位： | 北京航空航天大学仪器科学与光电工程学院,北京,100191 |
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| 摘 要： | 文章提出了VersaPHY的IP核的实现方案;根据VersaPHY协议,分析了VersaPHY的标签、数据包和寄存器,完成了VersaPHY的IP核设计;在Altera QuartusⅡ开发平台上,结合Verilog HDL语言和其自带的IP CORE实现了VP-Label寻址的数据包(读请求包、读响应包、写请求包、写响应包)的接收和发送;最后借助于QuartusⅡ集成开发环境提供的SignalTapⅡ逻辑分析仪进行验证,结果表明,该系统可以实现不同速度(100Mb/s、200Mb/s、400Mb/s、800Mb/s)的VersaPHY的数据包的传输,工作稳定可靠,满足实际应用需求。
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| 关 键 词： | VersaPHY IP核 Verilog HDL |
Design and implementation of IP Core of IEEE 1394b VersaPHY |
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| Zhu Yuhan
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Shao Hongfeng
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Yi Xiaosu
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Long Yingxue.Design and implementation of IP Core of IEEE 1394b VersaPHY[J].Computer Measurement & Control,2012,20(9):2525-2528. |
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| Authors: | Zhu Yuhan Shao Hongfeng Yi Xiaosu Long Yingxue |
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| Affiliation: | (School of Instrument Science and Opto-electronics Engineering,Beihang University,Beijing 100191) |
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| Abstract: | Implementations of VersaPHY IP core is presented.According to VersaPHY protocol,we analyse the VersaPHY labels,packages and register,and complete the design of VersaPHY IP core.In the Altera Quartus Ⅱ development platform,combining with the Verilog HDL language and its own IP CORE realizes the reception and transmission of packets addressed by VP-Label(read request,read response packet,a write request,write response packets).Finally we use SignalTap Ⅱ logic analyzers which is provided by Quartus Ⅱ integrated development environment to verify,the results show the functions of VersaPHY of IP core is implemented. |
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| Keywords: | VersaPHY IP core Verilog HDL |
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