Asymmetric dual-k spacer trigate FinFET for enhanced analog/RF performance

In this paper, we aim to explore the potential benefits of using source side only dual-k spacer (Dual-kS) trigate FinFET structure to improve the analog/RF figure of merit (FOM) for low power operation at 20 nm gate length. It has been observed from the results that Dual-kS (inner spacer high-k) FinFET structure improves the coupling of the gate fringe field to the underlap region towards the source side and results into improvement in transconductance \((g_{m})\) and output conductance \((g_{ds})\). It was also found that drain side only dual-k spacer (Dual-kD) improves the coupling of the gate fringe field to the underlap region towards the drain side which helps to shift away the drain field from gate edge and results into improvement in output conductance \((g_{ds})\) only at the cost of increase in Miller capacitance. A comparative simulation study has been performed on four different device structures namely both side low-k spacers (conventional), both side dual-k spacer (Dual-kB), Dual-kD and Dual-kS structures. From the simulation study, it was found that that Dual-kS structure has potential to improve \(g_{m}\) by \(\sim \)8.7 %, \(g_{ds}\) by \(\sim \)32.24 %, intrinsic gain \((A_{V0})\) by \(\sim \)11.44 %, early voltage \((V_{EA})\) by \(\sim \)47.59 %, maximum oscillation frequency (\(f_{MAX}\)) by \(\sim \)1.7 % and the ratio of gate-source capacitance and gate-drain capacitance \((C_{gs}/C_{gd})\) by \(\sim \)15.27 % with a slight reduction in the value of unity gain cut-off frequency (\(f_{T}\)) by \(\sim \)0.58 % in comparison to the conventional structure at drain current \((I_{ds})\) of \(10\,\upmu \)A/\(\upmu \)m. Furthermore, to reduce the drain field influence on the channel region, we also studied the effect of asymmetric drain extension length on Dual-kS FinFET structure.