GaInAs junction FET with InP buffer layer prepared by selective ion implantation of Be and rapid thermal annealing |
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Authors: | Selders J. Wachs H.J. Jürgensen H. |
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Affiliation: | Technical University of Aachen, Institute of Semiconductor Electronics, Aachen, West Germany; |
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Abstract: | ![]() GaInAs JFETs were fabricated on VPE-grown GaInAs layers. The pn junctions have been realised with Be ion implantation and rapid thermal annealing. The devices show a high transconductance of 130 mS/mm and an electron saturation velocity of 1.8 × 107 cm/s. Channel mobilities measured at the complete device are as high as 6800 cm2/Vs. These excellent device properties are due to the use of an undoped InP buffer layer which avoids the diffusion of Fe from the substrate into the active layer. The data were supported by S-parameter measurements which gave a frequency limit of 20 GHz for gate dimensions of 1.6 by 200 ?m2. |
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