异步FIFO的Verilog HDL设计

使用异步FIFO(First-In First-Out)同步源自不同时钟域之间的数据是在数字IC设计中经常用的方法。本文对异步FIFO进行了分析和研究,采用格雷码指针将地址指针同步到另一时钟域中,利用将地址分区的方法来判断空满状态。用Verilog HDL硬件描述语言对电路进行RTL级设计,使用Modelsim进行功能仿真,最后用FPGA通过了验证。

The design of asynchronous FIFO with verilog HDL

Asynchronous FIFO(First-In First-Out)is a general way to communicate between different clock domains digital IC design.This thesis makes an analysis and research for asynchronous FIFO memory,using gray code pointers and dividing the address space into some quadrants to distinguish between full and empty.The design is based on the verilog HDL language,and the results of model sim simulation and FPGA verification both indicate the design is feasible.