面向RTL的VHDL语言模拟系统设计与实现

设计并实现了一种面向寄存器传输级的VHDL语言模拟系统(RTL-based VHDL Simulator,RVS).介绍了RVS系统的处理流程和组成模块.RVS系统定义了面向寄存器传输级的VHDL语言子集,在编译阶段采用了一种基于递归的自顶向下语法分析算法,在模拟阶段采用了一种具有调试功能的基于进程的事件驱动模拟调度算法.RVS系统在Windows平台下用Visual Studio 2003进行了实现.实验表明,RVS系统对组合逻辑控制和微程序控制的SAP-CPU设计电路文件进行了正确地编译和模拟.

Design and Implementation of RTL-Based VHDL Simulator

Register Transfer Level (RTL)-based VHDL Simulator is proposed and implemented, named RVS. The RVS' s flow, composition modules as well as their functions is described. Firstly, the RTL subset of VHDL language in RVS is defined. Furthermore, a top-down syntax analysis algorithm based on recursion is developed during the compilation phase. During the simulation phase, an event-driven schedule algorithm based on process is proposed with debugging functions. We give the implementation of RVS in Windows OS and Visual Studio 2003. Finally, the experiment and analysis show that the compiler and simulator of RVS perform well and produce encouraging solutions correctly on two SAP-CPU designs controlled by combinational logic and micro-program.