基于两层流水线结构的FIR滤波器设计

本文提出了一种基于两层流水线体系结构的FIR滤波器的实现方案(2HPFIR).采用比输入采样频率快几倍的内部时钟频率,实现了乘加器件的高度复用,进而缩减了芯片面积.根据滤波器的抽头数目N和内部时钟快于采样频率的倍数M,在二层流水线结构的抽头链中,加入N/M-1个抽头把运算分成N/M个组.在流水线结构的组内形成M个阶段,组间形成N/M个阶段.随着抽头数量的增长,此结构很容易扩展,且不会增加关键路径的延时.此方法可以灵活应用到其它类似的专用滤波器设计中.

FIR Filters Design Based on Two-Hierarchy Pipeline Structure

This paper introduces a two hierarchy pipeline structure for FIR filters design.It is a flexible ASIC architecture for user specified symbol rate.By adopting the inner clock several times faster than the input data sampling rate,multiplying and adding component can be highly shared to reduce the area.In light of the number of taps of the filter N and the multiple of inner clock frequency to sampling rate M,N/M 1 taps should be added in the chain of taps in this two hierarchy pipeline architecture,which separate computations into N/M groups.The two hierarchies of pipeline are in group with M stages and between group with N/M stages respectively.As the number of taps of filter increases,the structure can be easily extended without increasing the delay of critical path.This method is flexible and can be adopted in other similar application specific filters design.