| 射频识别芯片设计中时钟树功耗的优化与实现 |
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| 引用本文： | 常晓夏,潘亮,李勇.射频识别芯片设计中时钟树功耗的优化与实现[J].中国集成电路,2011,20(9):36-39,68. |
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| 作者姓名： | 常晓夏 潘亮 李勇 |
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| 作者单位： | 北京中电华大电子设计有限责任公司,北京,100102 |
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| 摘 要： | UHF RFID是一款超高频射频识别标签芯片,该芯片采用无源供电方式,对于无源标签而言,工作距离是一个非常重要的指标,这个工作距离与芯片灵敏度有关,而灵敏度又要求功耗要低,因此低功耗设计成为RFID芯片研发过程中的主要突破点。在RFID芯片中的功耗主要有模拟射频前端电路,存储器,数字逻辑三部分,而在数字逻辑电路中时钟树上的功耗会占逻辑功耗不小的部分。本文着重从降低数字逻辑时钟树功耗方面阐述了一款基于ISO18000-6Type C协议的UHF RFID标签基带处理器的的优化和实现。
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| 关 键 词： | 时钟树低功耗设计 射频识别 时钟偏移 时钟延迟 插入延迟 |
The CTS Power Optimization Method in RFID Design Implementation |
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| CHANG Xiao-xia,PAN Liang,LI Yong.The CTS Power Optimization Method in RFID Design Implementation[J].China Integrated Circuit,2011,20(9):36-39,68. |
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| Authors: | CHANG Xiao-xia PAN Liang LI Yong |
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| Affiliation: | CHANG Xiao-xia,PAN Liang,LI Yong (Beijing Huada Electronic Design Inc. Ltd,100102 China) |
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| Abstract: | UHF RFID tag chip refers to Ultra High Rrequency RF Identification tag chip which applies passive power system.As for passive tag,working distance is an important index which related with sensitivity,in order to promote sensitivity,the power which include RF frontend circuit,memory and digital logic circuit need to be reduced.Usually, CTS power contributes a lot to digital logic power consumption.In this paper,we discribe the CTS power reduction optimization method and implementation of this UHF RFID chip based on ISO 18000-6 Type C protocol. |
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| Keywords: | Low power CTS design RFID clock skew latency insertion delay |
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