On the leverage of high-fT transistors foradvanced high-speed bipolar circuits |
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Authors: | Chuang CT Chin K Stork JMC Patton GL Crabbe EF Comfort JH |
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Affiliation: | IBM Thomas J. Watson Res. Center, Yorktown Heights, NY; |
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Abstract: | A detailed study on the leverage of high-fT transistors for advanced high-speed bipolar circuit applications is presented. It is shown that for the standard ECL (emitter-coupled logic) circuit, the leverage of high fT is limited by the passive resistors (emitter-follower resistor and collector load resistor) and wire delay, especially in the low-power regime. For the standard NTL (nonthreshold logic) circuit, the leverage is higher due to its front-end configuration and lower power supply value. As the passive resistors are decoupled from the delay path in various advanced circuits utilizing active-pull-down schemes, the leverage of high FT becomes more significant |
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