A 440-ps 64-bit adder in 1.5-V/0.18-μm partially depleted SOItechnology |
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| Authors: | Stasiak DL Mounes-Toussi F Storino SN |
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| Affiliation: | IBM Corp., Rochester, MN; |
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| Abstract: | A 64-bit adder in 1.5-V/0.18-μm partially depleted SOI technology, CMOS8S, and techniques to maintain performance are described. CMOS7S SOI, a 1.8-V/0.22-μm partially depleted SOI technology, achieves a 28% speed increase over bulk CMOS7S, and CMOS8S SOI delivers an additional 21%. In a 660-MHz CMOS8S SOI processor, the adder compensates for floating body effects in SOI devices which cause history effects, bipolar currents, and lower noise margins on dynamic circuits |
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