Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors |
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| Affiliation: | 1. Department of CSIE, National Chiao Tung University, Hsinchu, Taiwan, ROC;2. Department of EE, National Chung Cheng University, Chiayi, Taiwan, ROC;3. Department of CSIE, National Chung Cheng University, Chiayi, Taiwan, ROC;1. Department of Industrial Engineering (D.I.In.), University of Salerno, Fisciano, Salerno, Italy;2. Advanced System Technology-STMicroelectronics International N.V., Plan-les-Quates, Switzerland;3. Advanced System Technology-STMICROELECTRONICS, Agrate Brianza, Milano, Italy;1. School of Electrical Engineering, KAIST, Daejeon 305-701, Korea;2. Synopsys Inc., Mountain View, CA 94043, USA;3. School of Electrical and Computer Engineering, UNIST, Ulsan 689-798, Korea;1. iPack Vinn Excellence Center, School of Information and Communication Technology, Royal Institute of Technology (KTH) Electrum 229, 164 40 Stockholm-Kista, Sweden;2. School of Information Science and Technology, Fudan University, Shanghai, China |
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| Abstract: | Voltage scaling is an effective technique to reduce power consumption in processor systems. Unfortunately, timing discrepancies between L1 caches and cores occur with the scaling down of voltage. These discrepancies are primarily caused by the severe process variations of a few slow SRAM cells. Most previous designs tolerated slow cells by adjusting access latency based on a coarse-grained track of cache blocks. However, these methods become insufficient when the amount of slow cells increases. This paper addresses the issue for an 8T SRAM cache and proposes a cross-matching cache that includes dynamic timing calibration and actual bit-level timing-failure toleration. |
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| Keywords: | Cache memory Low voltage Timing discrepancy Timing-failure tolerance |
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