A 35-ns 128K/spl times/8 CMOS SRAM

A 128 K/spl times/8-b CMOS SRAM with TTL input/output levels and a typical address access time of 35 ns is described. A novel data transfer circuit with dual threshold level is utilized to obtain improved noise immunity. A divided-word-line architecture and an automatic power reduction function are utilized to achieve a low operational power of 10 mW at 1 MHz, and 100 mW at 10 MHz. A novel fabrication technology, including improved LOCOS and highly stable polysilicon loads, was introduced to achieve a compact memory cell which measures 6.4/spl times/11.5 /spl mu/m/SUP 2/. Typical standby current is 2 /spl mu/A. The RAM was fabricated with 1.0-/spl mu/m design rules, double-level polysilicon, and double-level aluminum CMOS technology. The chip size of the RAM is 8/spl times/13.65 mm/SUP 2/.