A 3.3 V, 10 Bits, Clock-Feedthrough Compensated Switched-Current Second Order Sigma-Delta Modulator |
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Authors: | Mourad Loulou Dominique Dallet Nouri Masmoudi Philippe Marchegay Lotfi Kamoun |
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Affiliation: | (1) AGH University of Science and Technology, Cracow, Poland |
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Abstract: | This article presents a low-pass sigma-delta modulator for Analogue-to-Digital conversion. The circuit uses a switched-current technique which presents a well known drawback called clock feedthrough. This phenomenon induces an error on the output signal value. In order to cancel the clock feedthrough effect, we use a new method based on a current feedback loop. The circuit is designed in 0.8 μm AMS “Austria Mikro Systems” single poly CMOS process. Measurements of the modulator are performed under A/D converters characterisation system, and show 55 dB dynamic range at 2.048 MHz sampling rate with 8 kHz input frequency bandwidth. These characteristics are suitable for audio applications. |
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