Modified stable Euler-number algorithm implementation for real-time image binarization

The stable Euler-number-based image binarization has been shown to give excellent visual results for images containing high amount of image noise. Being computationally expensive, its applications are limited mostly to general-purpose processors and in application specific integrated circuits. In this paper a modified stable Euler-number-based algorithm for image binarization is proposed and its real-time hardware implementation in a Field Programmable Gate Array with a pipelined architecture is presented. The proposed modifications to the algorithm facilitate hardware implementation. The end result is a design that out-performs known software implementations. The amount of noisy pixels introduced during the binarization process is also minimized. Despite the stable Euler-number-based image binarization being computationally expensive, our simulations show that the proposed architecture gives accurate results and this in real time and without consuming all chip resources.