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| H.264中二进制算术编码的硬件实现 | |
| 引用本文： | 陈传东,陈新. H.264中二进制算术编码的硬件实现[J]. 现代电子技术, 2007, 30(22): 48-50 |
| 作者姓名： | 陈传东 陈新 |
| 作者单位： | 福州大学,物理与信息工程学院,福建,福州,350002 |
| 基金项目： | 福建省科技厅集成电路(IC)技术平台建设项目 |
| 摘 要： | H.264标准中的二进制算术编码算法复杂,用软件实现起来速度慢,编码一个信号需要多个时钟周期。结合硬件实现特点,对算法流程进行合理优化,采用流水线设计方法,电路结构采用Verilog HDL进行RTL级描述,在Synplify平台上进行FPGA综合,介绍了H.264中二进制算术编码的FPGA实现方案。编码速度达到1 b/cycle,工作频率达到75.7 MHz,完全可以应用于视频图像的实时编码中。 |
| 关 键 词： | 二进制算术编码 |
| 文章编号： | 1004-373X（2007）22-048-03 |
| 收稿时间： | 2007-05-23 |
| 修稿时间： | 2007-05-23 |
Hardware Realization of Binary Arithmetic Coding for H.264 |
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| CHEN Chuandong,CHEN Xin. Hardware Realization of Binary Arithmetic Coding for H.264[J]. Modern Electronic Technique, 2007, 30(22): 48-50 | |
| Authors: | CHEN Chuandong CHEN Xin |
| Affiliation: | Physics and Information Engineering College, Fuzhou University, Fujian, 350002, China |
| Abstract: | The binary arithmetic coding in H.264 is complex and in a low speed realized by software,it needs much period of encoding a signal.By using pipeline design method,the working flow is optimized according to hardware realization.The architecture is described by Verilog HDL on the RTL level,and is synthesized and tested by FPGA.It can encode a binary symbol each cycle and can work at a speed of 75.7 MHz and can be used in the video compression system. |
| Keywords: | H.264 CABAC FPGA |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ | |