| 基于FPGA数字乘法器的设计 |
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| 引用本文： | 王文理 王丽 田云霞. 基于FPGA数字乘法器的设计[J]. 数字社区&智能家居, 2006, 0(2): 122-123 |
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| 作者姓名： | 王文理 王丽 田云霞 |
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| 作者单位： | 河北大学电子信息工程学院,河北保定071002 |
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| 摘 要： | 数字乘法器是目前数字信号处理中运用最广泛的执行部件之一，本文设计了三种基于FPGA的数字乘法器．分别是移位相加乘法器、加法器树乘法器和移位相加-加法器树混合乘法器。通过对三种方案的仿真综合以及速度和面积的比较指出了混合乘法器是其中最佳的设计方案。
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| 关 键 词： | FPGA 移位相加乘法器 加法器树乘法器 移位相加-加法器树混合乘法器 |
| 文章编号： | 1009-3044（2006）05-0122-02 |
| 收稿时间： | 2005-12-05 |
| 修稿时间： | 2005-12-05 |
Design of Digital Multiplier Based on FPGA |
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| WANG Wen-li, WANG Li, TIAN Yun-xia. Design of Digital Multiplier Based on FPGA[J]. Digital Community & Smart Home, 2006, 0(2): 122-123 |
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| Authors: | WANG Wen-li WANG Li TIAN Yun-xia |
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| Abstract: | The digital multiplier is used as one of the most extensive execution parts while digital signal processing at present.This text has designed three kinds of digital multipliers based on FPGA,they are shift summation multiplier,addition device tree multiplier and shift summation-addition device tree mixed multiplier.Through the simulation-synthesizing of the three kinds of schemes and comparing the speed with the area,we has pointed that the mixed multiplier is the best design method among them. |
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| Keywords: | FPGA shift summation multiplier addition device tree multiplier shift summation-addition Device tree mixed multiplier. |
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