基于FPGA的AES核设计

AES在安全性、高性能、高效率、易用性和灵活性等方面都具有显著的优点,随着业界对计算性能要求的不断提高,在FPGA上实现AES加解密硬核的研究得到了越来越多的关注。在深入分析AES算法的基础上,提出了基于FPGA的AES全流水硬件核设计模型。模型中改进了ae数据块和轮运算的硬件设计结构,有效地提高了AES硬核的计算性能。在Altera公司EP4CE40F23C6FPGA上的硬件实现结果显示,该AES硬核的硬件资源消耗为6413个LE和80个M9K,工作频率为310MHz,计算吞吐率为9.92Gbps,获得了非常好的计算加速效果。

Design of AES Core Based on FPGA

AES has its remarkable advantages in security, high performance, high efficiency, ease of use, flexibility, etc. As the demand of computation performance increases, researches on AES's FPGA implementation are paid more attention to. Based on the analysis of AES algorithm, a FPGA based fully pipelined AES model is proposed. In this model, the structure of the ae data block and wheel computation are modified in order to improve the performance of the AES hardcore. The implementation results on Altera EP4CE40F23C6 FPGA show that the proposed AES hardcore can run at 310 MHz with the computation throughput of 9.92 Gbps at the cost of 6413 LE and 80 M9K.