A semi-synchronous SAR ADC |
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| Authors: | Tao Tong Pavan K. Hanumolu Gabor C. Temes |
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| Affiliation: | 1. School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR, 97331, USA
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| Abstract: | A semi-synchronous clocking scheme is proposed for successive approximation register (SAR) analog-to-digital converters (ADCs). The conversion time is dynamically allocated to the comparator decision and to the DAC settling in every bit cycle. This significantly improves the conversion speed. |
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