Hardware architectures for the Tate pairing over GF(2) |
| |
Authors: | Maurice Robert William Colin |
| |
Affiliation: | aDepartment of Electrical and Electronic Engineering, University College Cork, Cork City, Ireland |
| |
Abstract: | In this paper two different approaches to the design of a reconfigurable Tate pairing hardware accelerator are presented. The first uses macro components based on a large, fixed number of underlying Galois Field arithmetic units in parallel to minimise the computation time. The second is an area efficient approach based on a small, variable number of underlying components. Both architectures are prototyped on an FPGA. Timing results for each architecture with various different design parameters are presented. |
| |
Keywords: | Tate pairing Cryptography Hardware architecture BKLS/GHS algorithm |
本文献已被 ScienceDirect 等数据库收录! |