| 基于FPGA的FESH分组密码算法高速实现 |
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| 引用本文： | 王建新,周世强,肖超恩,张磊.基于FPGA的FESH分组密码算法高速实现[J].信息网络安全,2021(1). |
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| 作者姓名： | 王建新 周世强 肖超恩 张磊 |
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| 作者单位： | 北京电子科技学院电子与通信工程系;北京工商大学农产品质量安全追溯技术及应用国家工程实验室 |
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| 基金项目： | 国家重点研发计划[2017YFB0801803];农产品质量安全追溯技术及应用国家工程实验室开放课题[AQT-2018-YB5]。 |
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| 摘 要： | FESH分组密码算法为2019年全国密码算法竞赛中进入第二轮评选的密码算法。文章对该算法的FESH-128-128型进行Verilog HDL高速实现,在有限状态机的基础上对顶层模块采用流水线设计方法进行优化,通过寄存器存储中间数据,提高运行效率。实验结果表明,在软件Quartus Ⅱ 15.0上使用5CEFA7F31C6芯片进行综合设计,采用流水线设计方法进行优化后,算法最高运行速率达到296.74 MHz,相较于有限状态机实现提高了98.28%;吞吐率达到37.98 Gbps,相较于有限状态机实现提升了约33倍。
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| 关 键 词： | FESH 分组密码 Verilog HDL高速实现 流水线设计 |
High-speed Implementation of FESH Block Cipher Algorithm Based on FPGA |
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| WANG Jianxin,ZHOU Shiqiang,XIAO Chaoen,ZHANG Lei.High-speed Implementation of FESH Block Cipher Algorithm Based on FPGA[J].Netinfo Security,2021(1). |
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| Authors: | WANG Jianxin ZHOU Shiqiang XIAO Chaoen ZHANG Lei |
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| Affiliation: | (Department of Electronic and Communication Engineering,Beijing Electronics Science and Technology Institute,Beijing 100070,China;National Engineering Laboratory for Agri-product Quality Traceability,Beijing Technology and Business University,Beijing 100048,China) |
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| Abstract: | The FESH block cipher algorithm is the cipher algorithm that entered the second round of selection in the 2019 national encryption algorithm competition.In this paper,the FESH-128-128 type of the algorithm is implemented in Verilog HDL at a high speed.On the basis of the finite state machine,the top-level module adopts the pipeline design method to optimize,and the intermediate data is stored in the register to improve the operating efficiency.The results show that the 5CEFA7F31C6 chip is used for synthesis on the software Quartus Ⅱ 15.0,and the pipeline design method is used to optimize the maximum operating speed of 296.74 MHz,which is 98.28%higher than the finite state machine implementation;the throughput rate reaches 37.98 Gbps,which Compared with the finite state machine,the realization is improved by about 33 times. |
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| Keywords: | FESH block cipher high-speed implementation of Verilog HDL pipeline design |
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