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| 一种高效宽带数字下变频器的设计与实现 | |
| 引用本文： | 庞龙,宇文英,陈禾. 一种高效宽带数字下变频器的设计与实现[J]. 半导体技术, 2010, 35(6): 610-613. DOI: 10.3969/j.issn.1003-353x.2010.06.023 |
| 作者姓名： | 庞龙 宇文英 陈禾 |
| 作者单位： | 北京理工大学,信息与电子学院,雷达技术研究所,北京100081;中国网通(集团)有限公司石家庄市分公司,石家庄,050011 |
| 摘 要： | 针对雷达系统小型化和低功耗的应用需求,提出一种宽带雷达数字接收机中数字下变频器的设计方法.通过采用系统采样频率等于输入信号中心频率4倍的采样技术,结合混频器的特殊实现结构以及半带FIR滤波器抽头系数的特点,经过详细的理论推导后,给出该方法具体的硬件实现结构,能够显著降低数字下变频信号处理的复杂程度,有效减少对硬件逻辑资源,尤其是硬件乘法器的消耗.该方法在FPGA中实现时,与使用传统方法设计的数字下变频器相比,硬件逻辑资源消耗减少83.65%,功耗降低约110 mW.最后,设计实例结果验证了设计方法的正确性以及很好的工程实用性. |
| 关 键 词： | 抽头系数 半带滤波器 数字下变频 现场可编程逻辑门阵列 |
Design and Realization of Highly Efficient Broad Band Digital Down Converter |
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| Pang Long,Yu Wenying,Chen He. Design and Realization of Highly Efficient Broad Band Digital Down Converter[J]. Semiconductor Technology, 2010, 35(6): 610-613. DOI: 10.3969/j.issn.1003-353x.2010.06.023 | |
| Authors: | Pang Long Yu Wenying Chen He |
| Affiliation: | Pang Long1,Yu Wenying2,Chen He1(1.The Research Lab of Radar Technology,School of Information and Electronics,Beijing Institute of Technology,Beijing 100081,China,2.China Netcom Corporation LTD.Shijiazhuang Branch,Shijiazhuang 050011,China) |
| Abstract: | A designed method of DDC module in wide band radar digital receiver is proposed for the application requirements of miniaturization and low power consumption in radar system.Using the sampling technique that the system sampling frequency equaled to 4 times the intermediate frequency,combining with the special implemented structure of mixer and the tap coefficient characteristics of half-band FIR filter,the specific hardware structure was presented after detailed theoretical derivation.Signal processing comp... |
| Keywords: | tap coefficient half-band filter digital down converter FPGA |
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