| AES算法的并发错误检测方法及其VLSI实现 |
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| 引用本文： | 赵佳,韩军,曾晓洋,韩林.AES算法的并发错误检测方法及其VLSI实现[J].计算机研究与发展,2009,46(4). |
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| 作者姓名： | 赵佳 韩军 曾晓洋 韩林 |
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| 作者单位： | 复旦大学专用集成电路与系统国家重点实验室,上海,201203 |
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| 摘 要： | 提出了一种AES算法的抗差分差错分析的并发错误检测方法--二维奇偶校验方法.与原有的一维奇偶校验方法相比,该方法提供了更为优化的奇偶校验位设置,更重要的是能够同时检测水平和垂直方向上的奇数个错误,在保持了对单个错误的100%的覆盖率的同时,将对多个错误的覆盖率大大提升.由于水平和垂直校验位计算模块可以复用,因此与原有的一维奇偶校验方法相比,该方法增加的硬件开销很小,对硬件实现的关键路径和吞吐率都没有影响,是一种理想的低成本高效率的抗差分差错分析的并发错误检测方法.
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| 关 键 词： | 差分差错分析 二维奇偶校验 并发错误检测 高级加密标准 高覆盖率 低成本 |
A Two-Dimensional Parity-Based Concurrent Error Detection Method for AES Against Differential Fault Attack and Its VLSI Implementation |
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| Zhao Jia,Han Jun,Zeng Xiaoyang,Han Lin.A Two-Dimensional Parity-Based Concurrent Error Detection Method for AES Against Differential Fault Attack and Its VLSI Implementation[J].Journal of Computer Research and Development,2009,46(4). |
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| Authors: | Zhao Jia Han Jun Zeng Xiaoyang Han Lin |
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| Affiliation: | State Key Laboratory of ASIC and System;Fudan University;Shanghai 201203 |
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| Abstract: | A two-dimensional parity-based concurrent error detection method for AES algorithm against differential fault attack is proposed. It combines two traditional one dimension parity check methods together to check errors in two directions. A simulation has been conducted to compare the fault coverage of the method in this paper with that of traditional parity-based CED methods. Compared with previous parity-based CED methods, this scheme has a more optimized configuration in choosing the number and position of... |
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