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一种基于轮流扫描捕获的低功耗低费用BIST方法
引用本文:王伟征,邝继顺,尤志强,刘鹏.一种基于轮流扫描捕获的低功耗低费用BIST方法[J].计算机研究与发展,2012,49(4):864-872.
作者姓名:王伟征  邝继顺  尤志强  刘鹏
作者单位:1. 湖南大学信息科学与工程学院 长沙410082;长沙理工大学计算机与通信工程学院 长沙410114
2. 湖南大学信息科学与工程学院 长沙410082
基金项目:国家自然科学基金项目(60673085,60773207);中国科学院计算机系统结构重点实验室开放课题基金项目
摘    要:过高的测试功耗和过长的测试应用时间是基于伪随机内建自测试(BIST)的扫描测试所面临的两大主要问题.提出了一种基于扫描子链轮流扫描捕获的BIST方法.在提出的方法中,每条扫描链被划分成N(N>1)条子链,使用扫描链阻塞技术,同一时刻每条扫描链中只有一条扫描子链活跃,扫描子链轮流进行扫描和捕获,有效地降低了扫描移位和响应捕获期间扫描单元的翻转频率.同时,为检测抗随机故障提出了一种适用于所提出测试方法的线性反馈移位寄存器(LFSR)种子产生算法.在ISCAS89基准电路上进行的实验表明,提出的方案不但降低约(N-1)?N的平均功耗和峰值功耗,而且显著地减少随机测试的测试应用时间和LFSR重播种的种子存储量.

关 键 词:内建自测试  全扫描测试  可测性设计  低功耗测试  低成本测试  LFSR重播种

A Low-Power and Low-Cost BIST Scheme Based on Capture in Turn of Sub-Scan Chains
Wang Weizheng , Kuang Jishun , You Zhiqiang , Liu Peng.A Low-Power and Low-Cost BIST Scheme Based on Capture in Turn of Sub-Scan Chains[J].Journal of Computer Research and Development,2012,49(4):864-872.
Authors:Wang Weizheng  Kuang Jishun  You Zhiqiang  Liu Peng
Affiliation:1(College of Information Science and Engineering,Hunan University,Changsha 410082)2(College of Computer and Communication Engineering,Changsha University of Science and Technology,Changsha 410114)
Abstract:Scan-based pseudo-random BIST is currently one of the most popular structured design-for-testability(DFT) methodologies in very large scale integrated circuit test.However,excessive power dissipation and prohibitively long test time are two serious issues in this testing approach.Recently,various techniques have been proposed to address one of these issues.But few of them can deal with the two issues simultaneously.In this paper,a new scan-based BIST scheme,namely BIST scheme based on capture in turn of sub-scan chains(BCIT),is proposed.In this scheme,each scan chain is divided into N(N>1) sub-chains.During test,using scan chain disabling technique,all sub-chains in a scan chain are active in turn in both scan shift and capture cycles,i.e.only one sub-chain is active at a time.Thus,the switching activities in the scan cells can be limited to a low level.To detect random pattern resistant faults,an algorithm of LFSR seed generation,which is compatible with the proposed test scheme,is presented as well.Experimental results on ISCAS’89 benchmark circuits show that compared with the conventional BIST scheme,the proposed strategy can achieve not only about(N-1) N reductions of average and peak power,but also significant reduction of test application time and seed storage for LFSR reseeding.
Keywords:built-in self test  full scan testing  design for testability  low power testing  low cost test  LFSR reseeding
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