超大规模集成电路可调试性设计综述

随着硬件复杂度的不断提高和并行软件调试的需求不断增长,可调试性设计已经成为集成电路设计中的重要内容.一方面,仅靠传统的硅前验证已经无法保证现代超大规模复杂集成电路设计验证的质量,因此作为硅后验证重要支撑技术的可调试性设计日渐成为大规模集成电路设计领域的研究热点.另一方面,并行程序的调试非常困难,很多细微的bug无法直接用传统的单步、断点等方法进行调试,如果没有专门的硬件支持,需要耗费极大的人力和物力.全面分析了现有的可调试性设计,在此基础上归纳总结了可调试性设计技术的主要研究方向并介绍了各个方向的研究进展,深入探讨了可调试性结构设计研究中的热点问题及其产生根源,给出了可调试性结构设计领域的发展趋势.

Survey of Design-for-Debug of VLSI

Design-for-debug(DFD) has become an important feature of modern VLSI.On the one hand,traditional pre-silicon verification methods are not sufficient to enssure the quality of modern complex VLSI designs,thus employing DFD to facilitate post-silicon verification has attracted wide interests from both academia and industry;on the other hand,debugging parallel program is a world-wide difficult problem,which cries out for DFD hardware supports.In this paper,we analyze the existing structures of DFD comprehensively and introduce different fields of DFD for debugging hardware and software.These fields contain various kinds of DFD infrastructures,such as the DFD infrastructure for the pipe line of processor,the system-on-chips(SOC) and the networks on multi-cores processor.We also introduce the recent researches on how to design the DFD infrastructures with certain processor architecture and how to use the DFD infrastructures to solve the debug problems in these different fields.The topologic of the whole infrastructure,the hardware design of components,the methods of analyzing signals,the compressing and storing signals,the using of DFD infrastructure in debugging parallel program and post-silicon debugging are all introduced.Furthermore,some possible future directions of DFD research are given based on the state-of-the-art literatures and industrial requirements.