FH4-060型高分辨堆积拒绝门

本文介绍一种用于快闪烁探测器能谱测量系统的堆积拒绝门,其分辨时间好于10ns。线路采用更新计时器,定时电容的更新时间包含在门宽度之内,原则上电路无死时间,输入计数率无上限,特别适用于高计数率的场合。电路内附反符合控制输入和门信号放大器,可实现对多道分析器的堆积拒绝和反符合控制。

Model FH4-060 High Resolution Pile-up Rejection Gate

A pile-up rejection gate used for fast scintillation spectroscopy system is presented and its resolution time less than 10 ns. utilizing renovating timer and including the renovating time of the timing capacitance in the gate width, the circuit hasn't death-time in principle, and the allowable input pulse rate is unlimited. It is specially suitable for using in high pulse rate occasion. Appending a veto control and a gate signal amplifier in the circuit, MCA can be operated in both pile-up rejection mode and anticoincidence mode.