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| 微处理器设计中的时序验证及优化 | |
| 引用本文： | 朱宇耀,苏凯雄,陈建. 微处理器设计中的时序验证及优化[J]. 现代电子技术, 2012, 35(8): 147-149,153 |
| 作者姓名： | 朱宇耀 苏凯雄 陈建 |
| 作者单位： | 福州大学物理与信息工程学院,福建福州,350002 |
| 基金项目： | 福建省科技重大专题专项目(2009HZ0003-12010HZ0004-1);福建省科技厅重大专项(2011H6015) |
| 摘 要： | 为了解决微处理器设计中时序验证和性能优化问题,采取可综合代码设计到静态时序分析过程中针对关键路径进行处理的策略,完成了系统性能优化的完整流程。理论分析和实践结果证明,根据RTL级的静态时序分析结果进行系统关键路径的优化,可显著提高微处理器的总体性能,减少设计的迭代次数,缩短了设计的周期。 |
| 关 键 词： | 微处理器 关键路径 可综合代码设计 静态时序分析 |
Time sequence verification and optimization in microprocessor design |
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| ZHU Yuyao , SU Kaixiong , CHEN Jian. Time sequence verification and optimization in microprocessor design[J]. Modern Electronic Technique, 2012, 35(8): 147-149,153 | |
| Authors: | ZHU Yuyao SU Kaixiong CHEN Jian |
| Affiliation: | (Institute of Physics and Information Engineering,Fuzhou University,Fuzhou 350002,China) |
| Abstract: | In order to solve the problem of time sequence verification and performance optimization in the process of microprocessor design,the processing strategy for critical path is carried out in the process from synthesizable code design to static timing analysis to fulfil the full flow of system performance optimization.Theoretical analysis and practical results show that the optimizing design for critical path in systems according to the result of static time sequence analysis in RTL-level can significantly improve the overall performance of the microprocessor,reduce its iteration time,and shorten its design cycle. |
| Keywords: | microprocessor critical path synthesizable code design static time sequence analysis |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ | |