Δ∑模数转换器中数字抽取滤波器的设计

抽取滤波器是过采样模数转换器中的重要组成部分。低字率、高采样频率的数字调制信号被转换成高字率、奈奎斯特频率采样的信号。该文介绍了应用于不同过采样率的通用数字抽取滤波器的设计,适用于一阶到七阶的Δ∑调制器,输入字长从1bit到32bit。设计和实现了一个过采样率为256的数字抽取滤波器,应用于三阶级联的Δ∑调制器。该抽取滤波器包括:级联积分梳状滤波器、补偿滤波器和一个窄带有限冲击响应半带滤波器。滤波器系数都采用CSD(Canonic SignedDigit)码实现。多级多采样率信号处理电路被用来实现补偿和半带滤波。整个滤波器经过了FPGA验证,输出正弦波的信噪比达到了110dB。

Decimation Filter Design in Sigma-delta ADC

Decimation is an important component of oversampled analog-to-digital conversion(ADC).It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at Nyquist rate.This paper presents an efficient design and implementation of a digital decimation filter for various downsampling ratios,which can be applicable for sigma-delta modulator orders from 1 to 7,and input word length from 1 to 32 bits.The proposed decimation filter consists of Cascaded-Integrated-Comb(CIC) filter,compensation lowpass filter and narrow transition-band finite impulse response(FIR) filter using canonic signed digit(CSD) number system.Multi-stage multi-rate signal processing is used to implement compensation lowpass and half-band filters.As a design example, a decimation filter with a downsampling ratio of 256,which is applicable for third-order cascaded sigma-delta modulators is presented.