A high-speed 64K/spl times/4 CMOS DRAM using on-chip self-timing techniques

The duration of internal operation of this DRAM is controlled by on-chip self-timing signals. With this feature, the leading and trailing edges of the row address strobe are allowed to have timing windows of 16 and 11 ns, respectively, even at a minimum cycle time of 80 ns. A novel address decoding scheme, utilizing a combination of NMOS NOR row decoders, CMOS NAND column decoders, and common predecoders, is employed to realize a fast array access time and a small die. The RAM has been fabricated with a 1.2-/spl mu/m n-well CMOS technology, and has a 21.34-mm/SUP 2/ die. Typical row access and column address access times are 47 and 16 ns, respectively. The active power dissipation is 115 mW at 200-ns cycle time.