一种基于时序逻辑电路的延时开关设计

时序逻辑电路设计是《数字电子技术》课程中一个难度大、综合性高的部分,它综合了组合逻辑电路和时序逻辑电路的内容。在进行状态机设计时,随着输入逻辑变量的增加,状态数目将呈指数倍急剧增加,这会使整个设计变得复杂且容易出错。以一个延时开关控制器的设计为例,提出了一种状态机输入变量简化的方法,降低了设计过程的复杂程度。

Design of Time Delay Switch Based on Sequential Logic Circuit

The design of sequential logic circuit is the more difficult and more synthetic part of the digital electric technology,which synthesizes combinational logic circuit and sequential logic circuit.In the state machine designing,with the increase of input logic variables,the number of states will increase exponential sharply.Thus,the design will be more complex and be error.Taking an example of time delay switch design,a simplified method of state machine is proposed,the complexity of design process can be red...