| 基于FPGA的AES算法芯片设计实现 |
| |
| 引用本文： | 黄小苑,戴紫彬. 基于FPGA的AES算法芯片设计实现[J]. 微电子学与计算机, 2005, 22(8): 62-64,68 |
| |
| 作者姓名： | 黄小苑 戴紫彬 |
| |
| 作者单位： | 解放军信息工程大学电子技术学院,河南,郑州,450004 |
| |
| 摘 要： | 高级加密标准(AES)集安全性、高效性、灵活性于一身,研究其硬件实现具有很重要的应用价值.本文针对AES分组密码算法的结构特点,讨论了AES算法FPGA实现的优势,重点分析了加/脱密模块的实现方案,最后给出在Quartus Ⅱ下的仿真实验结果.
|
| 关 键 词： | 高级加密标准 流水线 现场可编程门阵列 专用集成电路 吞吐率 |
| 文章编号： | 1000-7180（2005）08-062-03 |
| 收稿时间： | 2005-01-17 |
| 修稿时间： | 2005-01-17 |
Design on FPGA Implementation of AES Algorithm Chip |
| |
| HUANG Xiao-yuan,DAI Zi-bin. Design on FPGA Implementation of AES Algorithm Chip[J]. Microelectronics & Computer, 2005, 22(8): 62-64,68 |
| |
| Authors: | HUANG Xiao-yuan DAI Zi-bin |
| |
| Abstract: | Algorithm for the Advanced Encryption Standard (AES) appears to be excellent in security, efficiency, and flexibility, so the importance of its hardware implementation is obvious. The advantage of using FPGA architecture to design a cryptographic chip is presented in the paper, which is based on the characteristics of algorithm for AES. The design of en/decryptographic module is described in detail. Software simulation is made by Quartus II. And synthesis re-sults are summarized. |
| |
| Keywords: | AES Pipeline FPGA ASIC Throughput |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
|
