| 一种CMOS双沿触发器的设计 |
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| 引用本文： | 郭中和,杨银堂,姬慧莲. 一种CMOS双沿触发器的设计[J]. 半导体技术, 2003, 28(4): 65-67,75 |
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| 作者姓名： | 郭中和 杨银堂 姬慧莲 |
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| 作者单位： | 西安电子科技大学微电子研究所,陕西,西安,710071;西安电子科技大学微电子研究所,陕西,西安,710071;西安电子科技大学微电子研究所,陕西,西安,710071 |
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| 摘 要： | 基于CMOS传输门,分析了单、双沿触发器的逻辑结构,分析了一种晶体管数较少的CMOS双沿触发器,并用PSPICE程序进行了模拟,结果表明这种双沿触发器具有完整的逻辑功能,且具有结构简单,延迟时间短和数据处理能力高的优点,另外,与传统的单沿触发器相比,其功耗大约减少了61%。
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| 关 键 词： | 单沿触发器 双沿触发器 数据选择器 传输门 |
| 文章编号： | 1003-353X(2003)04-0065-03 |
Design of CMOS double-edge-triggered flip-flop |
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| GUO Zhong-he,YANG Yin-tang,JI Hui-lian. Design of CMOS double-edge-triggered flip-flop[J]. Semiconductor Technology, 2003, 28(4): 65-67,75 |
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| Authors: | GUO Zhong-he YANG Yin-tang JI Hui-lian |
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| Abstract: | In this paper,the logic constructions of a double-edge-triggered flip-flop and a single-edge-triggered flip-flop are analyzed on the basis of CMOS transmission gate.We introduce a set ofnovel double-edge-triggered flip-flop which can be implemented with fewer transistors than anyprevious design. Simulation using SPICE shows that this DET-FF has ideal logic functionality, asimpler structure,lower delay time and higher maximum data rate .The power dissipation in the DET-FF and traditional SET-FF is compared via consideration and simulations and it is shown that theproposed DET-FF reduces power dissipation by 61 while keep the same date rate. |
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| Keywords: | single-edge-triggered flip-flop double-edge-triggered flip-flop multiplexer trans-mission gate |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
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