Towards a pipelined Prolog processor

This paper describes the design of a Prolog machine architecture and organization. Our objective was to determine the maximum performance attainable by a sequential Prolog machine for “reasonable” cost. The paper compares the organization to both general purpose micro-coded machines and reduced instruction set machines. Hand timings indicate a peak performance rate of 450 K LIPS (logical inferences per second) is well within current technology limitations and 1 M LIPS is potentially feasible.