High frequency wide range CMOS analogue multiplier

A new CMOS analogue cell which can be used to implement a four-quadrant multiplier circuit is introduced. Simulation results of the circuit using the MOSIS 2 mu m process parameters are given. The circuit has an input range of +or-4 V and linearity error less than 1% for inputs up to +or-3 V. The magnitude and phase response are very flat; even at 30 MHz the change in the magnitude is less than 0.086 dB (1%) and the phase shift is less than 5 degrees .<>