| 基于组合解压缩电路的多扫描链测试方法 |
| |
| 引用本文： | 董婕,胡瑜,韩银和,李晓维.基于组合解压缩电路的多扫描链测试方法[J].计算机研究与发展,2006,43(6):1001-1007. |
| |
| 作者姓名： | 董婕 胡瑜 韩银和 李晓维 |
| |
| 作者单位： | 1. 中国科学院计算技术研究所先进测试技术实验室,北京,100080;中国科学院研究生院,北京,100049
2. 中国科学院计算技术研究所先进测试技术实验室,北京,100080 |
| |
| 基金项目： | 国家研究发展基金;国家高技术研究发展计划(863计划);北京市科研项目;中国科学院基金 |
| |
| 摘 要： | 提出一种采用组合电路实现解压缩电路的压缩方法,只需少量的输入管脚,可以驱动大量的内部扫描链·该方法利用确定性测试向量中存在的大量的不确定位(X位),采用对测试向量进行切片划分和兼容赋值的思想,通过分析扫描切片之间的兼容关系来寻找所需的外部扫描输入管脚的最小个数·实验结果表明,它能有效地降低测试数据量·此外,通过应用所提出的解压缩电路,扫描链的条数不再受到自动测试仪的限制,因此能充分发挥多扫描链设计降低测试应用时间的优点·
|
| 关 键 词： | 扫描设计 测试数据量 解压缩电路 组合电路 兼容 |
| 收稿时间： | 06 16 2005 12:00AM |
| 修稿时间： | 12 12 2005 12:00AM |
A Multiple-Scan-Chain Test Approach Based on Combinational Decompression Circuits |
| |
| Dong Jie,Hu Yu,Han Yinhe,Li Xiaowei.A Multiple-Scan-Chain Test Approach Based on Combinational Decompression Circuits[J].Journal of Computer Research and Development,2006,43(6):1001-1007. |
| |
| Authors: | Dong Jie Hu Yu Han Yinhe Li Xiaowei |
| |
| Affiliation: | 1.Advanced Test Technology Laboratory, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100080; 2. Graduate University of Chinese Academy of Sciences, Beijing 100049 |
| |
| Abstract: | An on-chip decompressor is an efficient method to reduce test cost in multiple scan chain designs. In this paper, a new technique is investigated to implement the decompressor by utilizing combinational circuits. The proposed architecture drives a large number of internal scan chains with far fewer external input pins, thus delivering significant reductions in test data volume. Based on the analysis of compatible relationships among scan slices, the number of external scan inputs can be minimized. The effectiveness and applicability of the proposed scheme are demonstrated by experimental results. |
| |
| Keywords: | scan design test data volume decompressor combinational circuits compatibility |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
|
