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基于FPGA的线列阵波束形成器设计
引用本文:晏慧强,王妍婷.基于FPGA的线列阵波束形成器设计[J].电子与封装,2020(3):15-19.
作者姓名:晏慧强  王妍婷
作者单位:无锡中微亿芯有限公司
摘    要:波束形成是声纳探测系统中探测目标的主要技术手段,在现有设备中,主要采用DSP来实现。在用DSP实现波束形成算法的过程中,由于DSP本身的顺序执行架构,如果采用单片DSP处理,从输入信号到输出结果之间存在非常大的时间延迟,采用5片DSP处理则功耗增加为5倍,时延200 ms。采用FPGA,通过设计并行运算的程序结构来实现波束形成算法可以大大缩短算法实现的时间延迟,功耗也可以降低为采用DSP的1/10。设计的波束形成器采用100 MHz时钟,相比采用5片DSP,运算时间由200 ms缩短到10 ms左右,功耗降低为后者的1/5。

关 键 词:声纳  波束形成  DSP  FPGA

Design of Linear Array Beamformer Based on FPGA
YAN Huiqiang,WANG Yanting.Design of Linear Array Beamformer Based on FPGA[J].Electronics & Packaging,2020(3):15-19.
Authors:YAN Huiqiang  WANG Yanting
Affiliation:(East Technologies,Inc.,Wuxi 214072,China)
Abstract:Beamforming is the main technique for detecting targets in sonar detection system.In the existing equipment,DSP is mainly used to realize the beamforming algorithm.In the process of implementing beamforming algorithm with DSP,the sequential execution architecture of DSP itself is considered.If single-chip DSP processing is used,there is a very large time delay between input signal and output result.If five-chip DSP processing is used,the power consumption will increase to five times and the time delay will be 200 ms.By using FPGA and designing parallel operation program structure to realize beamforming algorithm,the time delay and power consumption can be greatly reduced to 1/10 of the results by DSP.The designed beamformer uses 100 MHz clock,which shortens the operation time from 200 ms to about 10 ms,and reduces power consumption to 1/5 of the results by five DSPs.
Keywords:sonar  beamforming  DSP  FPGA
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