基于CRT的低成本RSA芯片设计

提出了一种基于改进的Montgomery算法和中国剩余定理(CRT)的RSA签名芯片的VLSI实现.由于采用了新颖的调度算法,实现了用576b的模乘单元来完成1152b的RSA模幂运算,从而大大降低了芯片面积;此外,CRT的引入使得整个系统的数据吞吐率与传统的1024bRSA系统相当.实验结果显示:芯片完成一次1024b的模幂运算需要约1.2M个时钟周期,而芯片规模在54K个等效门以下;如果系统时钟频率选取40MHz,系统签名速率可以达到30Kbps.

A Low Cost RSA Chip Design Based on CRT

In this paper, a VLSI design and ASIC implementation of a pretty low cost RSA cryptosystem is presented, which is based on the modified Montgomery algorithm and the Chinese remainder Theory (CRT), By adopting a novel scheduling method, we realize 1152-bit modular exponentiation with 576-bit modular multiplier unit, which reduces the hardware complexity greatly. And by using the CRT technique, a comparable throughput with general 1024-bit RSA cryptosystem is achieved. The experimental result shows that a 1024-bit modular exponentiation calculation can be performed in about 1.2 mega cycles, and less than 54K gates are needed. With 40MHz system clock, a signature rate of over 30Kbps can be achieved.