A 2.5-Gb/s fully-integrated,low-power clock and recovery circuit in 0.18-μm CMOS

Based on the devised system-level design methodology,a 2.5-Gb/s monolithic bang-bang phase-locked clock and data recovery(CDR) circuit has been designed and fabricated in SMIC's 0.18-μm CMOS technology.The Pottb(a|¨)cker phase frequency detector and a differential 4-stage inductorless ring VCO are adopted,where an additional current source is added to the VCO cell to improve the linearity of the VCO characteristic.The CDR has an active area of 340×440μm~2,and consumes a power of only about 60 mW from a 1...