基于FIOS类型的Montgomery双域模乘器设计

针对FIOS类型的Montgomery模乘扩展算法的比特级-字级和字级-字级的两种实现形式进行研究,设计多处理单元的流水线组织结构实现算法,并对模乘器进行双有限域统一结构设计,使之能够同时支持两个有限域GF(p)和GF(2n)上的运算。最后对设计的两种模乘器用Verilog硬件描述语言进行代码描述,采用Synopsys公司的Design Compiler在Artisan SIMC 0.18μm typical工艺库下综合。实验结果表明,该模乘器不仅在运算速度和电路面积方面各具有优势,而且具有运算长度可变的灵活性。

Design of Montgomery multiplier based on FIOS in dual-field

At first the research on two types algorithm of FIOS included bit level-word level(BLWL) and word level-word level(WLWL) is performed,then the pipeline architecture of multiple processing unit is proposed to speed up operation.And the unified architecture is proposed to operate in both finite fields GF(p) and GF(2n).The two bit-word and word-word multipliers in this work are captured in Verilog and synthesized under 0.18 μm CMOS technology.The results indicate that the multiplier has not only advantages in speed and area,but flexibility in data length operation.