| 14 nm FinFET栅围寄生电容的建模与拟合 |
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| 引用本文： | 郑芳林,任佳琪,刘程晟,李小进,石艳玲,孙亚宾.14 nm FinFET栅围寄生电容的建模与拟合[J].微电子学,2017,47(5):706-709. |
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| 作者姓名： | 郑芳林 任佳琪 刘程晟 李小进 石艳玲 孙亚宾 |
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| 作者单位： | 华东师范大学 信息科学技术学院 电子工程系, 上海 200241,华东师范大学 信息科学技术学院 电子工程系, 上海 200241,华东师范大学 信息科学技术学院 电子工程系, 上海 200241,华东师范大学 信息科学技术学院 电子工程系, 上海 200241,华东师范大学 信息科学技术学院 电子工程系, 上海 200241,华东师范大学 信息科学技术学院 电子工程系, 上海 200241 |
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| 基金项目： | 国家自然科学基金资助项目(61574056,8) |
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| 摘 要： | 提出了一种基于保角映射方法的14 nm鳍式场效应晶体管(FinFET)器件栅围寄生电容建模的方法。对FinFET器件按三维几何结构划分寄生电容的种类,再借助坐标变换推导出等效电容计算模型,准确表征了不同鳍宽、鳍高、栅高和层间介质材料等因素对寄生电容的依赖关系。为了验证该寄生电容模型的准确性,对不同结构参数的寄生电容进行三维TCAD仿真。结果表明,模型计算结果与仿真结果的拟合度好,准确地反映了器件结构与寄生电容之间的依赖关系。
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| 关 键 词： | 鳍式场效应晶体管 TCAD 寄生电容 器件模型 |
| 收稿时间： | 2016/11/27 0:00:00 |
Modeling and Fitting of Gate-Around Parasitic Capacitance for14 nm FinFET Devices |
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| ZHENG Fanglin,REN Jiaqi,LIU Chengsheng,LI Xiaojin,SHI Yanling and SUN Yabing.Modeling and Fitting of Gate-Around Parasitic Capacitance for14 nm FinFET Devices[J].Microelectronics,2017,47(5):706-709. |
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| Authors: | ZHENG Fanglin REN Jiaqi LIU Chengsheng LI Xiaojin SHI Yanling and SUN Yabing |
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| Affiliation: | Dept. of Electronic Engineering, East China Normal University, Shanghai 200241, P. R. China,Dept. of Electronic Engineering, East China Normal University, Shanghai 200241, P. R. China,Dept. of Electronic Engineering, East China Normal University, Shanghai 200241, P. R. China,Dept. of Electronic Engineering, East China Normal University, Shanghai 200241, P. R. China,Dept. of Electronic Engineering, East China Normal University, Shanghai 200241, P. R. China and Dept. of Electronic Engineering, East China Normal University, Shanghai 200241, P. R. China |
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| Abstract: | The conformal mapping of electric field had been employed to develop an accurate parasitic capacitance model for 14 nm FinFET device. According to the device''s 3D geometry structure, the gate-around parasitic capacitors had been thoroughly classified. Then, the Cartesian coordinate had been transferred into the elliptic coordinate, and the equivalent fringe capacitance model could be built-up by some arithmetical operations. The final model could cover the various fin width, fin height, gate height and different materials of ILD. In order to validate the proposed model, the comparisons between the proposed calculation and the 3D-TCAD simulation had been carried out. The results showed that the proposed model could match the gate-around parasitic capacitance of 3D FinFET device. The dependence between the device''s structure and the parasitic capacitance was illustrated well. |
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| Keywords: | FinFET TCAD Parasitic capacitance Device model |
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