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Power model for DCFL family |
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| Authors: | Garcia J. Hernandez A. del Pino J. Sendra J.R. Gonzalez B. Nunez A. |
| Affiliation: | Appl. Microelectron. Res. Inst., Univ. of Las Palmas de Gran Canaria; |
| Abstract: | A model to estimate power consumption in GaAs direct coupled FET logic (DCFL) family, which is based on sensitivity computations, is reported. Comparisons against SPICE simulations show errors smaller than 5% in power consumption estimation, while CPU time is reduced by more than two orders of magnitude |
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