CSD-RNS-based Single Constant Multipliers

Architectures for designing single constant multipliers in Residue Number System (RNS) for moduli of the 2 ⁿ −1, 2 ⁿ and 2 ⁿ  + 1 forms are introduced with the constant operand being recoded in Signed-Digit representation. Two methodologies are proposed. In the first one a straightforward implementation of the shift-and-add algorithm is adopted, while in the second one a graph-based approach is used. Both methodologies result in circuits that are shown to be efficient in terms of area and delay.